In association with an increase in the degree of integration of LSI chips, there has been strong demand for a reduction in package size. Under the circumstances, various package structures have been proposed. In recent years, developments have been carried out intensively for stacking semiconductor bare chips through utilization of through-silicon vias formed therein. Meanwhile, dual-face packages of real chip size are also highly likely to be commercialized. Conventional dual-face packages of any technology require a through-silicon via structure (refer to Patent Document 1). Since existing insulation methods for through holes in a semiconductor substrate involve high-temperature treatment, application of such insulation methods to a semiconductor packaging process is difficult. Formation of through holes in a semiconductor substrate and insulation for the through holes still involve problems to be solved; therefore, wiring that does not require through-silicon vias is desired.
Patent Document 2 discloses a lead-frame-type double-sided electrode package in which the package is vertically penetrated by a lead frame. However, since the arrangement of electrodes on the lower face of the package is identical with that of electrodes on the upper face of the package, the package has no flexibility in connection between the upper and lower faces.
Patent document 3 discloses a BGA-type double-sided electrode package in which electrodes penetrating through a substrate are provided so as to form a double-sided electrode structure. However, since electrode placement portions on the upper surface are the penetrating electrodes themselves, the package has no flexible in a pattern of connection with an upper-side IC.
Patent Document 4 discloses a double-sided electrode structure in which protrusion electrodes are formed on a substrate. However, Patent Document 4 discloses neither a method of forming the protrusion electrodes nor a connection method. Although Patent Document 4 discloses rewiring on the upper surface, the disclosed method for effecting rewiring is a conventional method in which a low-resistance metallic film is formed through upper surface plating, and a pattern is formed by use of lithography. Therefore, the disclosed double-sided electrode structure has a big problem in terms of cost.
Patent Document 1: Japanese Patent Application Laid-Open (kokai) No. 2001-127243
Patent Document 2: Japanese Patent Application Laid-Open (kokai) No. 2003-249604
Patent Document 3: Japanese Patent Application Laid-Open (kokai) No. 2005-235824
Patent Document 4: Japanese Patent Application Laid-Open (kokai) No. 2002-158312